The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.
Metal pads, such as probe pads or wire bonding pads, have been used for various IC applications. In order to perform its functions properly, a metal pad should have sufficient size and strength to withstand physical stress due to such actions as probing or wire bonding. However, the ever-decreasing geometry size of ICs has dictated the shrinking of metal pads too, and often traditional metal pads may suffer from problems such as difficulty in bonding with bonding wires, peeling, or cracking in layers below the metal pads. To address some of these issues, a big via (many times larger than a regular via) can be used to provide support for a metal pad. Nevertheless, existing processes of forming such big vias may have certain drawbacks. For example, due to severe dishing or polishing erosion effects, existing processes to form big vias may lead to passivation bubbles, which may result in device defects.
Therefore, while existing methods of forming big vias have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.